A typical prior art semiconductor transistor device is described with reference to FIG. 1, wherein a semiconductor wafer fragment 10 is shown. Wafer fragment 10 comprises a semiconductor material substrate 11, preferably silicon, and a transistor device 12 on the substrate 11.
Device 12 comprises a transistor gate 14, a channel region 42 beneath the transistor gate, and source and drain active regions 20 and 22, respectively, opposingly adjacent the channel region and operatively adjacent the transistor gate. By "operatively adjacent", it is meant that the source and drain active regions 20 and 22 function together with the transistor gate 14 to form an operating transistor device 12.
The source and drain active regions comprise relatively low conductivity regions 24 and 26, and relatively high conductivity regions 28 and 30. The relatively low conductivity regions 24 and 26 are source and drain Lightly Doped Diffusion (LDD) regions, respectively, and the relatively high conductivity regions are source and drain regions 28 and 30, respectively. The relative conductivity of regions 24, 26, 28 and 30 is determined by the amount of conductivity-enhancing dopant within the regions: The relatively low-conductivity LDD regions, 24 and 26, being less heavily doped than the relatively high-conductivity source and drain regions 28 and 30.
The source and drain active regions 20 and 22 have a polarity, and this polarity is determined by the type of transistor device 12 formed. If transistor device 12 is a P-channel Metal-Oxide Semiconductor field effect transistor (PMOS), then source and drain active regions 20 and 22 will comprise p-type conductivity enhancing dopant, and will accordingly have a p-type polarity. If, on the other hand, transistor device 12 is an N-channel Metal-Oxide Semiconductor field effect transistor (NMOS) device, source and drain active regions 20 and 22 will comprise n-type conductivity enhancing dopant and will accordingly have an n-type polarity.
Referring to the gate 14, gate 14 comprises an insulative oxide layer 32, and laterally opposing edges 34 and 36. Gate 14 will typically comprise several layers of material, including a polysilicon layer over the oxide layer 32, a metal silicide layer over the polysilicon layer and an insulative capping layer over the metal silicide layer. Adjacent edges 34 and 36 of gate 14 are insulative sidewalls 38 and 40.
In operation, source region 28 is biased relative to drain region 30, a voltage is applied to gate 14, and electrons flow between the source and drain regions 28 and 30 through channel region 42. Several problems can occur as the source and drain regions 28 and 30 are biased relative to one another. These problems include Drain-Induced Barrier Lowering (DIBL) and Hot Electron effects.
DIBL is normally observed when the source and drain are biased relative to one another, and when the gate voltage is well below a threshold voltage of the gate--the threshold voltage being the minimum voltage necessary to open channel 42 for relatively unimpeded electron flow between the source 28 and the drain 30.
Before explaining DIBL further, device 12 will be described in greater detail. Device 12 typically comprises two back-to-back diodes between source 28 and drain 30. For instance, if device 12 is an NMOS transistor device, source 28 and drain 30 are n-type regions and channel 42, between them is a p-type region. Thus, device 12 comprises a first diode, containing source 28 and channel 42, and a second diode, containing channel 42 and drain 30, in back-to-back orientation relative to one-another. Each diode will comprise a junction at the interface of the n-type and p-type regions, and each junction will have a potential energy barrier associated with it. Carriers of NMOS device 12 (the carriers being electrons) will need to overcome the potential barriers to travel from source 28 to drain 30. At low gate voltages, device 12 is off and a leakage current between source 28 and drain 30 is limited by the potential energy barriers of the junctions. When the gate voltage is increased, the potential energy barriers are lowered, enabling relatively unimpeded current flow from source 28 to drain 30, i.e., device 12 is turned on.
If channel 42 comprises a short length, the potential energy barrier of a junction can be reduced by a voltage at the drain, even when the voltage at the gate is low. Such drain-voltage induced reduction of a potential energy barrier is DIBL. Once a potential energy barrier is lowered, some of the carriers in the source can leak from source to body, creating an undesired source-to-body current flow, or leak from source to drain, creating an undesired subthreshold current. Accordingly, it is desired to decrease DIBL.
Hot electron effects occur when a surface potential beneath gate oxide 32 is lowered, permitting a subthreshold current flow in the channel region 42 at an oxide-substrate interface between gate oxide 32 and semiconductor substrate 11. A particularly undesired consequence of hot electron effects is that hot carriers at the oxide-substrate interface are occasionally ejected into gate oxide 32, damaging the gate oxide 32 and possibly becoming trapped in the gate oxide. Damage to the gate oxide due to hot carrier ejection accumulates over time, and will likely eventually shift a threshold voltage of device 12, and ruin the device 12. Accordingly, it is desired to decrease hot electron effects.
The above-discussed problems, DIBL and hot electron effects, are commonly referred to as short-channel effects because they tend to be most problematic in transistor devices having channels less than 2 microns long. As such short-channel transistors are becoming increasingly common through device miniaturization, it is desired to develop structures and methods which alleviate hot carrier effects in short-channel devices.
Other undesired aspects of presently-available short-channel devices pertain to the relatively limited domain over which there is a linear dependance of source-drain current on source-drain voltage. This problem is illustrated in Panel A of FIG. 4, which shows drain-source current (I.sub.DS) plotted against drain-source voltage (V.sub.DS), at varying gate-source voltages (V.sub.GS) of 0 volt, 1 volt, 2 volts, 3 volts, and 4 volts; for a transistor device with a gate length of about 0.6 microns. As shown, at V.sub.GS greater than zero, there tends to be a relatively short region wherein I.sub.DS is linearly dependant on V.sub.DS, after which I.sub.DS plateaus and remains relatively constant for increasing V.sub.DS. It would be desirable to create a longer domain of linear dependence of I.sub.DS on V.sub.DS for short-channel semiconductor devices.